[Buildroot] [PATCH for-next 01/11] arch/Config.in.riscv: add Zicsr and Zifencei standalone extensions
Romain Naour
romain.naour at gmail.com
Sun May 29 13:18:01 UTC 2022
Since gcc 12, default Riscv ISA spec version was bump to 20191213 [1].
This introduce a major incompatibility issue is the csr read/write
(csrr*/csrw*) instructions and fence.i instruction has separated from
the "I" extension, become two standalone extensions: Zicsr and
Zifencei; so you might get error messages like that: unrecognized
opcode "csrr" (or "fence.i").
Indeed, without Zifencei we can't build opensbi bootloader [3]:
opensbi-1.0/lib/sbi/sbi_tlb.c: Assembler messages:
opensbi-1.0/lib/sbi/sbi_tlb.c:190: Error: unrecognized opcode `fence.i', extension `zifencei' required
As a workaround, opensbi build system has been patched [4] to use
-march=rv64imafdc_zicsr_zifencei when needed.
This workaround doesn't work in Buildroot due to the local patch
0001-Makefile-Don-t-specify-mabi-or-march.patch removing -march
from CFLAGS.
Fix this issue by introducing two additional Kconfig option
enabling Zicsr and Zifencei standalone extensions for gcc >= 12
as recommanded by [2].
Select Zicsr and Zifencei for General purpose (G) architecture variant
(BR2_riscv_g) since theses extentions were implicitely enabled
previously.
[1] https://gcc.gnu.org/gcc-12/changes.html
[2] https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4
[3] https://github.com/riscv-software-src/opensbi/blob/v0.9/lib/sbi/sbi_tlb.c#L173
[4] https://github.com/riscv-software-src/opensbi/commit/5d53b55aa77ffeefd4012445dfa6ad3535e1ff2c
Signed-off-by: Romain Naour <romain.naour at gmail.com>
Cc: Mark Corbin <mark at dibsco.co.uk>
---
arch/Config.in.riscv | 21 ++++++++++++++++++++-
arch/arch.mk.riscv | 6 ++++++
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index 288ed833eb..91feea0918 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -18,6 +18,12 @@ config BR2_RISCV_ISA_RVD
config BR2_RISCV_ISA_RVC
bool
+config BR2_RISCV_ISA_RVZicsr
+ bool
+
+config BR2_RISCV_ISA_RVZifencei
+ bool
+
choice
prompt "Target Architecture Variant"
default BR2_riscv_g
@@ -29,8 +35,11 @@ config BR2_riscv_g
select BR2_RISCV_ISA_RVA
select BR2_RISCV_ISA_RVF
select BR2_RISCV_ISA_RVD
+ select BR2_RISCV_ISA_RVZicsr if BR2_TOOLCHAIN_GCC_AT_LEAST_12
+ select BR2_RISCV_ISA_RVZifencei if BR2_TOOLCHAIN_GCC_AT_LEAST_12
help
- General purpose (G) is equivalent to IMAFD.
+ General purpose (G) is equivalent to IMAFD
+ (with Zicsr and Zifencei since gcc >= 12).
config BR2_riscv_custom
bool "Custom architecture"
@@ -63,6 +72,16 @@ config BR2_RISCV_ISA_CUSTOM_RVD
config BR2_RISCV_ISA_CUSTOM_RVC
bool "Compressed Instructions (C)"
select BR2_RISCV_ISA_RVC
+
+if BR2_TOOLCHAIN_GCC_AT_LEAST_12
+config BR2_RISCV_ISA_CUSTOM_RVZicsr
+ bool "Control and Status Register (CSR) Instructions"
+ select BR2_RISCV_ISA_RVZicsr
+
+config BR2_RISCV_ISA_CUSTOM_RVZifencei
+ bool "Instruction-Fetch Fence"
+ select BR2_RISCV_ISA_RVZifencei
+endif
endif
choice
diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
index f3bf2b3467..294a5f90a9 100644
--- a/arch/arch.mk.riscv
+++ b/arch/arch.mk.riscv
@@ -26,5 +26,11 @@ endif
ifeq ($(BR2_RISCV_ISA_RVC),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
endif
+ifeq ($(BR2_RISCV_ISA_RVZicsr),y)
+GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr
+endif
+ifeq ($(BR2_RISCV_ISA_RVZifencei),y)
+GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zifencei
+endif
endif
--
2.35.3
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